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µDewy is archived and no longer developed. This is a snapshot of its documentation. → Dewy

B.2.1 Codegen Notes

The RISC-V backend uses the same basic strategy as x86_64: it preserves udewy's logical value-stack behavior, but keeps the shallow part of that stack in registers.

  • The current visible expression result stays in a0.
  • A small prefix of saved values is cached in callee-saved registers before deeper values spill to the real stack.
  • Calls place the first 8 arguments in a0-a7 and marshal any remaining arguments into an outbound stack area.
  • Call lowering maintains the required 16-byte stack alignment at the actual call instruction.
  • Busy locals live in s1, s5-s11 (across calls) or t2-t4 (between calls) through the shared local register allocation; ordinary builds only.
  • The visible value may be pending: a local not yet loaded (it then loads straight into its cache register or into t0 as a right operand), or a comparison whose operands are still in a0/t0. if, loop and short-circuit and tests branch on the operands directly (bge a0, t0, ...) instead of materializing -1/0; not on a pending comparison inverts it; everything else materializes first.